The present invention is generally directed toward the testing of digital logic computer circuits. More particularly, the present invention is directed towards a clock timing relationship during test that provides a means for testing such circuits for circuit delay faults and short path faults, as well as the more traditional stuck-at faults. Even more particularly, the present invention is directed to clocking means and a method for operating test circuits constructed in accordance with level sensitive scan design (LSSD) circuit construction methodology.
The increasing ability, from a technology point of view, of being able to position semiconductor logic devices in ever increasing densities on electronic chip substrates has lead to a great increase in circuit complexity. Because of this increase in complexity, it has become more difficult to test semiconductor chip devices, particularly such devices which are meant to implement digital computer logic circuits.
Accordingly, it has been found desirable to add to the circuits themselves mechanisms which provide on-chip test capabilities. These capabilities often find representation in the LSSD design rules wherein a block of logic is surrounded (logically if not physically) on two sides by shift register latch scan strings. These scan strings typically comprise a plurality of shift register latches (SRLs) each of which must have two latches, L1 and L2, which are connected in master-slave fashion. During normal functioning of the circuits, information signals are stored in the SRLs by one or more system clocks. During test operations, test patterns or bit sequences are shifted into these SRLs using their shift register mode of operation with separate shifting clocks. These test patterns are used as stimuli to the logic block. These signals are subsequently propagated through the logic block and are captured in a second set of master-slave latch pairs at a predetermined point in time. This point in time can be determined for the logic circuit block in a known technology since it takes a certain known amount of time for signals to propagate through the individual logic gates in the block.
Various clocking sequences are used during test operations. Sequences are used to scan input test data into the shift register latch scan string to provide input test signals to the circuit block being tested. Clock sequences may also be provided to launch signals from the input shift register latches into the inputs of the circuit block and also to capture responses from the outputs of the circuit block into a second set of latches. For purposes of understanding the present invention, however, it is not absolutely necessary that the second set of latches be configured in a scan string, although this is certainly desirable for scanning out the resulting test data in a serial fashion.
In the typical test operation of circuits built in accordance with LSSD design methodologies, a test pattern is scanned in to the slave latches in the shift register scan string. This is accomplished by shifting data along the latch pairs in the string so as to load data information in the slave latches of each latch pair. This data is used as excitation for the logic circuit whose output response is captured in a second set of master-slave latches (also preferably disposed in a scan string) located at the output of the logic circuit block being tested. One of the aspects of this form of testing is that at the end of the process of scanning in excitation data, each master-slave latch pair in the shift register scan string possesses the same data bit, that is, either a 0 or a 1. This mechanism provides tests for so-called stuck-at faults in which a signal on a net appears to be fixed and does not vary with changes to the input of the net. Because of this characteristic, these faults can be observed during low-speed testing.
While the above mentioned test procedures and methodology may be employed to perform tests for stuck-at faults in the circuit logic, they are inadequate for other kinds of tests which are very desirable.
In normal usage, it is desired to operate these computer circuits at high speeds. It is, therefore, desirable to provide minimal delay between the time that the computer clocking mechanisms launch the input data from the first set of latches and that later time when the responses to this data are captured in the second set of latches. This time delay is typically determined during the design process of the computer circuit by computing the maximum signal propagation delay through the block. In fact, it is common (if somewhat risky) to slightly overlap the launch and the capture clock pulses to improve the clock cycle of the computer circuits. However, this clock overlap causes a so-called race condition. If the logic block being tested has a path between input and output signal lines with a very short delay, a changing signal can be launched along this path and the resulting incorrect data captured in an output latch pair, all during the clock overlap. Such a short path or "sneak path" may have been originally designed into the logic block or may occur during manufacture as the result of the accumulation of "fast" circuits along the path. For whatever reason, it is desirable to determine, during post-manufacturing tests, whether or not such a short path exists.
In a similar manner, it is possible that there may exist, in the logic block to be tested, a signal path which is longer than designed for or desired. It would therefore be useful to also be able to test for this condition during test operations that occur subsequent to manufacture but prior to shipment of the circuit chip or its installation in a machine. Short path faults, as described above, and these long path or delay faults generally manifest themselves only during at-speed operation of the circuits.
It is seen, therefore, that while LSSD test methodologies are important in detecting stuck-at fault conditions, they are generally not useful in detecting short path or delay fault conditions, even though all of these faults are permanent errors in the logic.